A VLSI ARCHITECTURE FOR THE DES ALGORITHM

This section of the blog has been used to describe the proposed architecture for the data encryption standards algorithm . This section has also been used to describe detailed design of the various basic blocks of the architecture.

Basic view of the proposed architecture is shown as follows:

The three most important components of the des algorithm are :

• key generation

• controller

• encryption/decryption engine.

Round Keys Generation Process:

• Sixteen rounds are required to generate the sixteen round keys. First a 64-bit input key is provided to the permutation-1 block. The permutation-1 block performs permutation on the input key into 48-bit data, which are provided to two 28-bit blocks (C and D). After that, the two 28-bit data are circularly left shifted by one or two bits,

Controller for the Encryption/Decryption Operation

The controller has six different states, shown in a form of finite state machine:

• When the reset input is at logic ‘1’ , the machine enters in the Idle state and it generates two control signals, Sel_L_Mux and Sel_R_Mux. Both the control signals are kept at logic ‘0’ . When the En_De signal is logic high, the machine enters encryption mode and otherwise it enters decryption mode.

• In the encryption state, two control signals En_Counter and En_Encrypt both at logic ‘1’ level are generated. In the decryption state the En_Counter control signal is at logic ‘1’ and En_Encrypt control signal has logic ‘0’ level.

En_Encrypt is at logic ‘1’=UP COUNTER

En_Encrypt is at logic ‘0’= DOWN COUNTER

• After the encrypt state, comes the encrypt rounds state. Here the machine finishes its sixteen encryption rounds. En_Encrypt, Sel_L_Mux, Sel_R_Mux, En_L_Reg and En_R_Reg, are the signals that are generated in this round, all these are kept at logic high.

• After the decrypt state, comes the decrypt rounds state. Here the machine finishes its sixteen decryption rounds. En_Encrypt, Sel_L_Mux, Sel_R_Mux, En_L_Reg and En_R_Reg, are the signals generated in this round, En_Encrypt signal is kept at logic 0.

• Next state is the final result state.

Architecture for an S-Box

• The substitution operation includes a set of eight substitution boxes . Each S-Box takes in 6-bit input and it generates 4-bit output. The S-Boxes can be designed by using a set of five MUXs. architecture of s-box using mux based approach is shown below.

• Out of the 5 MUXs, the first 4 are 4 bit, 16:1 MUXs. These generate four rows of the S-box. These four MUXs are driven by the same select lines, which arrive from the middle 4 bits of the input to the s-box.

• The last mux is a 4-bit, 4:1 MUX. The MSB and LSB of the input form a 2 bit binary number. This number is used to select one out of the four outputs generated by the previous 4 MUXs.

• Therefore a 4 bit output signal (SBox_Out) is generated.

The Encryption/Decryption Operation

• When reset signal to the controller is at logic high, the controller enters an idle state and Sel_L_Mux and Sel_R_Mux signals are at logic 0. These selection lines are used for selecting inputs for MUX-L and MUX-R and routing them to the L_reg and R_reg registers respectively.

• When the signal EN_DE is logic 1, the controller resides in the Encrypt state and it makes En_Encrypt logic high and the architecture performs the encryption. Similarly, when EN_DE is at logic low in the Decrypt state, the architecture performs decryption.

• This architectures needs a 48-bit XOR gate. One of the input signals of the gate comes from the expansion permutation operation and the other signal is one of the sixteen, 48-bit round keys. The output of the XOR gate is provided to the substitution boxes (S-Boxes). The 32-bit output of the eight S-Boxes is then permutated, the permutated output is then XORed with the left 32-bits of the initial permutated 32-bits, which have been selected by the MUX-L. The output of the operation is then stored in the register R-Reg.

A detailed view of the proposed VLSI architecture for encryption/decryption using DES algorithm:

References:

J. G. Pandey, A. Gurawa, H. Nehra and A. Karmakar, "An efficient VLSI architecture for data encryption standard and its FPGA implementation," 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), Bangalore, 2016, pp. 1-5, doi: 10.1109/VLSI-SATA.2016.7593054. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7593054&isnumber=7593023

Author: Anvesh Pandey