Case Study: Results of FPGA Implementation of DES

The case study of different examples illustrated in the above blogposts has resulted in the observation of a stark difference between the experimental and methodical approaches.

Cryptography intends to secure information that is being communicated. So, ideally through a set of rules that govern cryptography allows only those intended—and no one else—to receive the information to access and process it. In its very essence, cryptography is the study of encryption and decryption algorithms.

As the technologies in-place evolve and new ones come into existence, data security becomes necessary. Thus encryption, decryption assume indispensable roles in many applications, such as common communication, health-monitoring and biometric data based recognition systems that need short-term data security.

So in the previous blogposts we saw high-performance, low cost and area-efficient VLSI implementation of lightweight ciphers for the purpose of encryption.

Now let us dive into the nitty gritty of the subject while taking a look at the results these approaches yield.

Reiterating, in operation, the Encryption Decryption signal EN_DE is at logic ‘1’ for the encryption. The very signal is set at logic ‘0’ for performing the decryption operation. Further, to make an estimate of the complete hardware resources needed, a fully loop-unrolled DES algorithm implementation is shown.

In addition, the proposed architecture completes each of the encryption/decryption rounds in one clock cycle. As depicted in the figure below, the encryption/decryption operation requires nineteen clock cycles.

The architectures require a 48-bit XOR gate for signal ‘E_XOR_K’. One of the input signals of the gate comes from the expansion permutation operation (E) and the other signal is one of the sixteen, 48-bit round keys. The output of the XOR gate is provided to the substitution boxes (S-Boxes). The 32-bit output of the eight S-Boxes is then permutated (P).As per (2), the permutated output is then XORed with the left 32-bits of the initial permutated 32-bits, which have been selected by the MuxL.

So, in its very essence, this design would utilize almost 14.55 times lesser multiplexers and 16 times lesser XOR gates. Now we all know how important it is, to have an efficient hardware architecture that uses minimum resources. This design helps us to bring efficiency and minimalism through its implementation.

The FPGA device utilization of the synthesized design shows that it utilizes, 1.07 % FPGA slices, 29.22 % Bounded. IOBs and 3.13 % of total BUFG elements. A synthesized RTL schematic view of the proposed architecture is put below. The signal has been set at logic ‘0’ for performing the decryption operation. The design has been thoroughly verified by providing sample vectors in the form of uniform random numbers for plaintext and cipher keys. The proposed architecture completes each of the encryption/decryption rounds in one clock cycle. Further, to make an estimate of the complete hardware resources need a fully loop-unrolled DES algorithm implementation is done, using only 1.07 % slice LUTs.

On a conclusive note, let us run through the important takeaways of this chain of blogposts. In the first blog post of this series we saw the proposed simple and efficient VLSI architecture for computation of DES algorithm. The proposed architecture requires nineteen clock cycles to encrypt a plaintext into ciphertext. The decryption process is identical to encryption operation and it completes the decryption process in nineteen clock cycles. The key generation process is realized in a combinational data-path and it provides all the required sixteen round keys to the encryption/decryption block in the first cycle of the clock.

In the DES algorithm, sixteen rounds are required to generate the sixteen round keys. To start the round key generation process, first a 64-bit input key is provided to the permutation choice-1 (permutation-1) block. The permutation-1 block permutes the input key into 48-bit data, which are provided to two 28-bit blocks. After that, the two 28-bit data are circularly left shifted by one or two bits, which depends upon the number of round as per the DES key generation algorithm. The encryption/decryption operation is managed by the controller, which is explained below.

Then, come the second blog post, we saw how the proposed architecture works for both encryptions as well as for decryptions, which depends upon the input signal ‘EN_DE’. When the signal EN_DE is at logic ‘1’, the controller resides in the Encrypt state and it asserts En_Encrypt to logic high. The architecture performs the encryption operation. In the Decrypt_Rounds state, the machine completes sixteen decryption rounds, which are required as per the DES algorithm

Similarly, when EN_DE is at logic low in the Decrypt state, the architecture performs decryption operation.

And in this culminative blog post describing the case study performed, we saw how data encryption standard (DES) is well-suited for the implementation of low-cost, extremely efficient and lightweight cryptography applications. We also saw how an efficient VLSI architecture for DES algorithm based encryption/decryption engine is designed and implemented.

And most importantly we saw how depending upon the encryption/decryption needs, the same set of architecture performs both encryption and decryption operations, which is something very unique. This can be one major takeaway you can bank on, for this series of blog posts.

Well, on a very kernel fundamental level, we also summarized the IEEE paper which depicts that the hardware synthesis result design utilizes only 1.07 % slice LUTs, 0.31 % slice registers and 29.22 % of bonded FPGA device fabric. Isn't that wonderful? I absolutely think it is.

This means that the design we performed case-study on is pretty efficient and self-providing in itself.